DESIGN OF POWER-EFFICIENT TRUE SINGLE PHASE CLOCKING FLIP-FLOP USING 19 –TRANSISTOR BASED ON LOGIC STRUCTURE REDUCTION SCHEME

Abstract

 Flip flops are fundamental storage components employed widely in digital system designs,
which apply intense pipelining methods and utilise numerous FF-rich modules, such as register files, shift
registers, and FIFO, in order to store information. The power consumption of the FFs and clock distribution
networks used in a typical digital system design There are just 19 transistors needed to create an ultralow-
power, genuine single-phase clocking FF in this project. Master-slave logic is used in the design, which
incorporates both static-CMOS and complementary pass-transistor logic. It is used to minimise the
number of transistors needed to provide high power and delay performance in the design. Despite the
circuit's simplicity, no internal nodes are allowed to float during operation in order to prevent power
leakage. Improved time performance is achieved via a virtual VDD design method that speeds up state
transitions in the slave latch. The power delay product is taken into account while designing transistors
(PDP).